This invention relates to CMOS integrated circuits, and more particularly to an improved CMOS masterslice that provides, on a single chip: (1) memory elements that are readily accessable through a plurality of data ports, and (2) logic functions that can be easily customized for a particular need. The present invention therefore discloses a very versitle CMOS masterslice that can be used with a wide variety of high speed processor applications.
In recent years, CMOS (Complimentary Metal-Oxide Semiconductor) technology has become increasingly popular among circuit designers because of its low power consumption, high noise immunity, and operation over a wide power supply range. Further, a variety of new MSI and LSI functions, such as memories, microprocessors, A/D and D/A converters, telecommunication circuits, and the like, has placed CMOS among the most prominent semiconductor technologies. (For purposes of this application, MSI refers to medium scale integration integrated circuits. MSI circuits are generally considered as having at least 50-100 individual logic elements therein. LSI refers to large scale integration, and represents integrated circuits having at least 500-1000 individual logic elements therein.)
Despite the significant advantages offered by CMOS integrated circuits, the use of CMOS technology for many high speed applications has been limited because of the relatively slow operating speed of CMOS compared to other semiconductor technologies such as TTL (transistor-transistor logic) and ECL (emitter coupled logic). Although significant improvements have been made within the past few years with respect to improving the operating speed of CMOS, presently existing CMOS integrated circuits still impose undesireable limitations for the logic designer, expecially from an overall systems point of view. For example, most logic applications, especially those relating to processors, require the cyclic transfer of data from one storage device to another, typically with a intermediate processing step (i.e., the data must be shifted, added or subtracted from other data, or otherwise processed in some fashion). If such a transfer must be done quickly--at very high speeds--then existing CMOS circuits, such as memory and logic chips, are generally unsuitable because of their inherent long propagation delays between devices as a consequence of off-chip drive requirements. That is, data must be driven from the memory chip to a functional logic chip or chips (where the data can be processed), and then driven back to the memory chip. These CMOS off-chip drive requirements thus represent a significant speed limiting factor.
One approach used to minimize off-chip drive requirements, and thereby increase the speed of operation, is to put as much circuitry as possible on one chip. Hence, LSI and VLSI (very large scale integration, typically having greater than 5,000-10,000 logic elements on one chip) devices have been developed for high speed applications. Not only do such LSI and VLSI devices offer improved speed, but they also generally provide increased reliability (fewer number of parts within the system; fewer interface requirements; etc.) as well as greater packaging flexibility from a system point of view (the circuits provide more functions in a smaller space). Unfortunately, these advantages are available only at an increased cost--such LSI and VLSI are only realizable after spending a great amount of money and development time. Moreover, such devices are, by necessity, customized for a particular design application. Thus, once developed, after expending a considerable amount of engineering and processing time, these customized and inflexible devices may only be used for one application. Further, because of the huge expense involved in the development of such customized LSI and VLSI circuits, it is generally not practical to commence development of such devices unless there is some assurance that a large quantity of such devices will eventually be needed. As a practical matter, therefore, the use of customized LSI and VLSI circuits for many applications, especially lower quantity applications, is not available because either the expense is too great, or because there is insufficient development time available.
In order to alleviate the long developmental times and large expenses associated with customized LSI and VLSI devices, it is known in the art to use gate arrays to provide the logic designer with a means of quickly and less expensively customizing integrated circuits for a particular need. Gate arrays, for purposes of this application, may be considered as integrated circuits that contain arrays of logic gates or elements (realized in CMOS technology with complementary transistor pairs) that may be selectively interconnected, in a final or semi-final process step, to realize a desired logic function. As such, the lengthy and expensive developmental effort associated with designing and fabricating the logic gates or elements on a suitable substrate need only be carried out once, while the developmental effort associated with interconnecting the logic gates, realized for example by adding a metalization layer, may be customized for a particular application in a relatively short period of time and thereafter readily integrated with the final or semifinal process steps of the device.
Unfortunately, the use of gate arrays, at least the use of the type of gate arrays employed in the prior art, is generally inefficient because not all logic gates or elements are used once the gates are interconnected for a particular application. Thus, the gate array circuit device will typically end up being larger for a given application than it would be if it were realized using fully customized circuitry. For example, it is not uncommon for 40-50% of the available circuitry within a gate array device to go unused. Ideally, of course, less than 10 to 20% of such circuitry would go unused if the available space on the substrate material is to be efficiently used.
Prior art CMOS memory devices, while typically providing efficient use of available substrate space, nonetheless present some serious limitations with respect to the system architecture. That is, such memory devices, such as commercially available RAMs (random access memories) only allow one memory location to be accessed at any given time. Thus, while access to the memory is random, the access steps must typically be performed serially. This, of course, slows down operation of the overall system. Further, such commercially available RAMs represent another chip that presents off-chip drive requirements for the other integrated circuits employed within the system. As explained above, these off-chip drive requirements also reduce the system operating speed.
From the foregoing, it is evident that there is a need in the art for an integrated circuit device that not only offers the traditional advantages of LSI CMOS circuits (including low power, high noise immunity, wide range of power supply operation, high speed, improved reliability, and efficient use of available space), but that also offers the design flexibilities associated with gate arrays and flexible architecture schemes. The invention disclosed herein is directed towards a device that addresses these needs.
Accordingly, it in an object of the present invention to provide a new CMOS masterslice that offers improved design and memory access flexibility while still offering the advantages of traditional LSI CMOS circuitry (low power consumption, high noise immunity, wide range of power supply operation).
A further object of the present invention is to provide such a CMOS masterslice that may be easily, quickly, and relatively inexpensively customized to suit the needs of a particular application.
Still a further object of the present invention is to provide such a CMOS masterslice that exhibits improved speed of operation.
An additional object of the present invention is to provide a CMOS masterslice that includes an array of memory cells that can be easily and randomly accessed for reading or writing through a plurality of data and address ports, including the capability of accessing two different memory cells simultaneously at the same or at different data rates.
Still another object of the present invention is to provide such a new CMOS masterslice in a compact, efficient package that requires a minimum number of input/output (I/O) pads for interfacing with other integrated circuit packages.